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ISL6532A
Data Sheet November 2002 FN9099.0
P RE LIM IN AR Y
3-in-1 ACPI Regulator/Controller for Dual Channel DDR and DDR2 Memory Systems
The ISL6532A provides a complete ACPI compliant power solution for dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller and integrated LDO to supply VDDQ with high current during S0/S1 (Run) states and standby current during S3 (suspendto-RAM = STR) state. During Run mode, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. A buffered version of the VDDQ/2 reference is provided as VREF. The VDDQ PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter incorporates simple, single feedback loop, voltage-mode control with fast transient response. Both the switching regulator and standby LDO provide a maximum static regulation tolerance of 2% over line, load, and temperature ranges. VDDQ is user-adjustable by means of external resistors down to 0.8V. Switching VDDQ power control between the PWM regulator and the standby LDO during state transitions is accomplished smoothly via the ISL6532A's ACPI control circuitry. The NCH signal provides synchronized switching of a backfeed blocking switch during the transitions. An integrated soft-start feature brings VDDQ into regulation in a controlled manner when returning to Run mode from S4/S5 (suspend-to-disk = STR) or mechanical off states. During S0 the PGOOD signal indicates that all supplies are within spec and operational. Each output is monitored via the FB pins for under and overvoltage events. Current limiting is included on the VTT and VDDQ standby regulators. Thermal shutdown is integrated.
Features
* Generates 3 Regulated Voltages - Synchronous Buck PWM Controller with Standby LDO - 1.8A Integrated Sink/Source Linear Regulator with accurate VDDQ/2 divider reference. - LDO regulator for 1.5V Video and Core voltage * ACPI compliant sleep state control * Glitch-free transitioning during state changes * Integrated VREF Buffer * PWM Controller Drives Low Cost N-Channel MOSFETs * 12Volt Direct Drive Saves External Components * 250kHz Constant Frequency Operation * Excellent Output Voltage Regulation - Both Outputs: 2% Over Temperature * 5V or 3.3V Down Conversion * Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications * Simple Single-Loop Voltage-Mode PWM Control Design * Fast PWM Converter Transient Response * Under and Over-voltage Monitoring of VDDQ and VTT Outputs * Current Limited VTT regulator * Integrated Thermal Shutdown Protection
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Pinout
ISL6532A (QFN) TOP VIEW
SLP_S5# SLP_S3# UGATE LGATE GNDP P12V NCH 21 PGOOD 20 PHASE 19 DRIVE2 GND 18 FB2 17 GNDA 16 COMP 15 FB 8 VDDQ 9 10 11 12 13 14 VTT_SENSE P3V3SBY OCSET VDDQ VREF_OUT VREF_IN
Ordering Information
PART NUMBER TEMP. RANGE (oC) 0 to 70 PACKAGE 6X6mm 28ld QFN PKG. NO.
28 27 26 25 24 23 22 GNDP 5VSBY 1 2 3 4 5 6 7
ISL6532ACR
L28.6X6
Applications
* Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs * Graphics cards - GPU and memory supplies * ASIC power supplies * Embedded processor and I/O supplies * DSP supplies
GNDQ GNDQ VTT VTT VDDQ
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Block Diagram
P3V3SBY VOLTAGE REFERENCE 0.800V 0.680V (-15%) 5V 12VCC POR EA2 0.920V (+15%)
SLP_S3#
SLP_S5#
5VSBY
VDDQ S3 REGULATOR
VDDQ(3)
2
S3 UV/OV2 UV/OV PWM ENABLE S0 S0/S3 SLEEP, SOFT-START, PGOOD, AND FAULT LOGIC SOFT-START PWM EA1 COMP OSCILLATOR 250kHz PWM LOGIC UV/OV1 OC COMP 20A PGOOD FB COMP OCSET
VTT_SENSE
DRIVE2
VTT REG
VTT(2)
FB2 NCH
GNDQ
DISABLE
ISL6532A
RU
{
12V POR P12V UGATE
VREF_IN
RL
{
PHASE
GNDA LGATE
VREF_OUT
GNDP
ISL6532A Simplified Power System Diagram
5VSBY 12V 5V
ISL6532A
NCH SLP_S3 SLP_S5 SLEEP STATE LOGIC PWM CONTROLLER Q2 Q1 VDDQ +
5VSBY/3V3SBY STANDBY LDO
VDDQ LINEAR CONTROLLER
VREF VTT REGULATOR + VTT
Q3 VAGP +
Typical Application - VDDQ From 5 or 3.3V
5VSBY +3.3V +12V CBP 3V3SBY +5V or +3.3V
PGOOD VDDQ VREF SLP_S3 SLP_S5 VREF_OUT VREF_IN + UGATE PHASE NCH + ROCSET Q1 LOUT + LGATE Q2 CVDDQ_OUT
OCSET
CIN VDDQ 2.5V
VTT + VDDQ CVTT_OUT
VTT VTT
ISL6532A
VDDQ VTTSENSE GNDQ
Q2 VAGP 2.5V + COUT2
DRIVE2 FB COMP FB2 GNDP GNDA
3
ISL6532A Typical Application - VDDQ From 5V Dual
5VSBY +3.3V +12V CBP 3V3SBY 5V Dual
PGOOD VDDQ VREF SLP_S3 SLP_S5 VREF_OUT VREF_IN UGATE PHASE OCSET ROCSET Q1 LOUT + LGATE VDDQ Q2 CVDDQ_OUT VDDQ 2.5V + CIN NCH
VTT + VDDQ CVTT_OUT
VTT VTT
ISL6532A
VTT_SENSE Q2 VAGP 2.5V + COUT2 GNDP GNDA FB2 DRIVE2 FB COMP
GNDQ
4
ISL6532A
Absolute Maximum Ratings
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC For Recommended Soldering Conditions, See Intersil Tech Brief TB334.
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V 10% Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Supply Voltage on 3V3SBY . . . . . . . . . . . . . . . . . . . . . +3.3V 10% Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply Current ICC0 ICC3 ICC5 S0 S3 S5 5 TBD 800 A mA
POWER-ON RESET
Rising 5VSBY POR Threshold Falling 5VSBY POR Threshold Rising P12V POR Threshold Falling P12V POR Threshold TBD TBD TBD TBD V
OSCILLATOR AND SOFT-START
PWM Frequency Ramp Amplitude Error Amp Reset Time VDDQ Soft-Start Interval fOSC VOSC tRESET tSS Mechanical Off/S5 to S0 Mechanical Off/S5 to S0 225 3.73 3.73 250 1.5 4.14 4.14 275 4.55 4.55 kHz V ms ms
REFERENCE VOLTAGE
Reference Voltage System Accuracy VREF 0.792 -2.0 0.800 0.808 +2.0 V %
PWM CONTROLLER ERROR AMPLIFIER
DC Gain Gain-Bandwidth Product Slew Rate GBWP SR Guaranteed By Design 15 80 6 dB MHz V/s
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source UGATE and LGATE Sink IGATE IGATE -1 1 A A
5
ISL6532A
Electrical Specifications
PARAMETER Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
NCH BACKFEED CONTROL
NCH Current Sink NCH Trip Level INCH VNCH NCH = 0.8V 8.55 9.0 8 9.45 mA V
VDDQ STANDBY LDO
Output Drive Current 3V3SBY > 3.0V 450 mA
VTT REGULATOR
Sink/Source Current Current Limit Upper Divider Impedance Lower Divider Impedance Divider Impedance Matching VREF_OUT Buffer Source Current ILIMIT RU RL RU/RL IVREF_OUT 5VSBY > 4.5V 2.2 1.8 2.5 2.5 TBD 2.4 5 A A k k % mA
LINEAR REGULATOR DC GAIN Gain Bandwidth Product Slew Rate DRIVE2 High Output Voltage DRIVE2 Low Output Voltage DRIVE2 High Output Source Current DRIVE2 Low Output Sink Current PGOOD
PGOOD Rising Threshold PGOOD Falling Threshold PGOOD Threshold Hysteresis VVTT_SENSE/VVDDQ S0 VVTT_SENSE/VVDDQ S0 57.5 45.0 TBD % % % GBWP SR Guaranteed By Design 15 9.5 -.7 .85 80 6 10.3 0.1 -1.4 1.2 1.0 dB MHz V/s V V mA mA
PROTECTION
OCSET Current Source VDDQ OV Level VDDQ UV Level Linear Regulator OV Level Linear Regulator UV Level Thermal Shutdown Limit IOCSET VFB/VREF VFB/VREF VFB2/VREF VFB2/VREF TSD S0 S0 S0 S0 20 115 85 115 85 140 A % % % % C
6
ISL6532A Functional Pin Description
This section provides a description of each of the 28 pins of the ISL6532A as shown in Figure1.
SLP_S5# SLP_S3# UGATE LGATE
UGATE (Upper FET Gate Drive)
UGATE drives the upper (control) FET of the VDDQ synchronous buck switching regulator. UGATE is driven between GND and P12V.
GNDP
LGATE (Lower FET Gate Drive)
NCH
P12V
28 27 26 25 24 23 22 GNDP 5VSBY GNDQ GNDQ VTT VTT VDDQ 1 2 3 4 5 6 7 8 VDDQ 9 10 11 12 13 14 VTT_SENSE P3V3SBY OCSET VDDQ VREF_OUT VREF_IN GND 21 PGOOD 20 PHASE 19 DRIVE2 18 FB2 17 GNDA 16 COMP 15 FB
LGATE drives the lower (synchronous) FET of the VDDQ synchronous buck switching regulator. LGATE is driven between GND and P12V.
FB (Feedback) and COMP (Compensation)
The VDDQ switching regulator employs a single voltage control loop. FB is the negative input to the voltage loop error amplifier. The positive input of the error amplifier is connected to a precision 0.8V reference and the output of the error amplifier is connected to the COMP pin. The VDDQ output voltage is set by an external resistor divider connected to FB. With a properly selected divider, VDDQ can be set to any voltage between the power rail (reduced by converter losses) and the 0.8V reference. Loop compensation is achieved by connecting an AC network across COMP and FB. The FB pin is also monitored for under- and over-voltage events.
FIGURE 1. 28 LEAD QFN TERMINAL ASSIGNMENTS
5VSBY (5 Volt Standby)
5VSBY is the primary supply to the state and control logic and to the analog references and blocks of the ISL6532A. It is typically connected to the 5V standby rail of an ATX power supply. During S5 sleep states the ISL6532A enters a reduced power mode and draws less than 1mA (ICC5) from the 5VSBY supply. The supply to 5VSBY should be locally bypassed at the pin
PHASE
Connect this pin to the upper MOSFET's source. This pin is used to monitor the voltage drop across the upper MOSFET for over-current protection.
OCSET
Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 20A current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation:
I OCSET xR OCSET I PEAK = ------------------------------------------------r DS ( ON )
P12V (12V Power)
P12V provides the gate drive to the upper (control) and lower (synchronous) FETs of the PWM power stage. The VTT regulation circuit and the Linear Driver are also powered by P12V. P12V is not required except during S0/S1 operation. P12V is typically connected to the +12V rail of an ATX power supply.
P3V3SBY (3.3V or 5V Standby)
The VDDQ standby regulator supply is fed from the P3V3SBY pin. The regulator is capable of providing standby VDDQ power from either a 3.3V or 5V source.
An over-current trip cycles the soft-start function.
VDDQ
The VDDQ pins should be connect externally together to the regulated VDDQ output. During S0/S1 (Run) states, the VDDQ pins serve as inputs to the VTT regulator and to the VTT Reference precision divider. During S3 (Suspend to RAM) state, the VDDQ pins serve as an output from the integrated standby LDO.
GNDA, GNDP, GNDQ (Ground)
The GND terminals of the ISL6532A provide the return path for all power supplies. High ground currents are conducted directly through the exposed paddle of the MLFP package which must be electrically connected to the ground plane through a path as low in inductance as possible. GNDA is the Analog ground pin, GNDQ is the return for the VTT regulator and GNDP is the return for the upper and lower gate drives.
VTT
The VTT pins should be connect externally together. During S0/S1 states, the VTT pins serve as the outputs of the VTT linear regulator. During S3 state, the VTT regulator is disabled.
7
ISL6532A
VTT_SENSE
VTT_SENSE is used as the feedback for control of the VTT linear regulator. Connect this pin to the VTT output at the physical point of desired regulation.
Functional Description
Overview
The ISL6532 contains complete control, drive, protection and ACPI compliance for powering DDR memory systems. It is designed for microprocessor computer applications with 5VATX, 12VATX, 5VSBY, and optionally 3.3VSBY from an ATX power supply. A 250kHz Sychronous Buck Regulator with a precision 0.8V reference provides the proper VDDQ voltage to the DDR system. An internal LDO regulator with the ability to both sink and source current and an externally available buffered reference that tracks the VDDQ output by 50% provides the VTT termination voltage to the DDR system. ACPI compliance is realized through the SLP_S3 and SLP_S5 sleep signals and through monitoring of the 12V ATX bus.
VREF_OUT
VREF_OUT is a buffered version of VTT and also acts as the reference voltage for the VTT linear regulator. It is recommended that a minimum capacitance of 0.1F is connected between VDDQ and VREF_OUT and also between VREF_OUT and GND for proper operation.
VREF_IN
A capacitor, CSS, connected between VREF_IN and Ground is required. This capacitor, in combination with the Upper Divider Impedance (RU), sets the time constant for the start up ramp when transitioning from S3 to S0. The minimum value for CSS can be found through the following equation:
C VTTOUT V DDQ C SS > ----------------------------------------------20 R U
Initialization
The ISL6532 automatically initializes upon receipt of input power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input bias supply voltage. The POR monitors the bias voltage at the 5VSBY and P12V pins. The POR function initiates soft-start operation after the bias supply voltages exceed their POR thresholds.
NCH (Blocking N-FET Driver)
NCH is an open-drain output that controls the MOSFET that blocks backfeed from VDDQ to the 3V or 5V rail during S3 state. When the VDDQ PWM regulator is inhibited NCH will be held low. If NCH is not actively utilized, it still must be tied to the 12V rail
State Transitions
Cold Start (Mechanical Start or S5 to S0 Transition) At the onset of a mechanical start, the ISL6532 receives it's bias voltage from the 5V Standby bus (5VSBY). As soon as the SLP_S3 and SLP_S5 have transitioned HIGH, the ISL6532 starts an internal counter. Following a cold start or any subsequent S5 state, state transitions are ignored until the system enters S0/S1. None of the regulators will begin the soft start procedure until the 5V Standby bus has exceeded POR, the 12V bus has exceeded POR and VNCH has exceeded the trip level. Once all of these conditions are met, the PWM error amplifier will first be reset by internally shorting the COMP pin to the FB pin. This reset lasts for 2048 clock cycles, which is typically 8.2ms. The digital soft start sequence will then begin. The PWM error amplifier reference input is clamped to a level proportional to the soft-start voltage. As the soft-start voltage slews up, the PWM comparator generates PHASE pulses of increasing width that charge the output capacitor(s). The internal VTT LDO will also soft start through the reference that tracks the output of the PWM regulator. The soft start lasts for 2048 clock cycles, which is typically 8.2ms. This method provides a rapid and controlled output voltage rise. Figure 2 shows the soft start sequence for a typical cold start. Due to the soft start capacitance, CSS, on the
PGOOD (Power Good)
Power Good is an open-drain logic output that changes to a logic low if any of the three regulators are out of regulation in S0 state. PGOOD will always be low in any state other than S0.
SLP_S5# (S5 Sleep Signal)
This is an input signalling the S5 state.
SLP_S3# (S3 Sleep Signal)
This is an input signalling the S3 state.
FB2
Connect the ouput of the external linear regulator to this pin through a properly sized resistor divider. The voltage at this pin is regulated to 0.8V. This pin is monitored for under- and over-voltage events.
DRIVE2
Connect this pin to the gate terminal of an external NChannel MOSFET transistor. This pin provides the gate voltage for the linear regulator pass transistor. It also provides a means of compensating the error amplifier for applications requiring the transient response of the linear regulator to be optimized.
8
ISL6532A
standby regulator, enable the VTT LDO and force the NCH pin to a high impedance state turning on the blocking MOSFET. The internal short between the VTT reference and the VTT rail is released. Upon release of the short, the capacitor on VREF_IN is then charged up through the internal resistor divider network. The VTT output will follow this capacitor charge up and acts as the S3 to S0 transition soft start for the VTT rail. The PGOOD comparator is enabled only after 2048 clock cycles, or typically 8.2ms, have passed following the S3 transition to a HIGH state. Figure 3 illustrates a typical state transition from S3 to S0. S3 S5
12VATX 2V/DIV VDDQ 500mV/DIV VTT 500mV/DIV
S3 S5
12VATX 2V/DIV 5VSBY 1V/DIV VDDQ 500mV/DIV
VTT 500mV/DIV PGOOD
5V/DIV
2048 Clock Cycles 2048 Clock Cycles
12V POR
Soft Start Initiates
Soft Start Ends PGOOD Comparator Enabled
FIGURE 2. TYPICAL COLD START
VREF_IN pin, the S5 to S0 transition profile of the VTT rail will have a more rounded features at the start and end of the soft start whereas the VDDQ profile has distinct starting and ending points to the ramp up. By directly monitoring 12VATX and the SLP_S3 and SLP_S5 signals the ISL6532 can achieve PGOOD status significantly faster than other devices that depend on Latched_Backfeed_Cut for timing. Active to Sleep (S0 to S3 Transition) When SLP_S3 goes LOW with SLP_S5 still HIGH, the ISL6532 will disable the VTT linear regulator, enable the VDDQ standby regulator and disable the VDDQ switching regulator. NCH is pulled low to disable the backfeed blocking MOSFET. PGOOD will also transition LOW. When VTT is disabled, the internal reference for the VTT regulator is internally shorted to the VTT rail. This allows the VTT rail to float. When floating, the voltage on the VTT rail will depend on the leakage characteristics of the memory and MCH I/O pins. The VDDQ rail will be supported in the S3 state through the standby VDDQ LDO. When S3 transitions LOW, the Standby regulator is immediately enabled. The switching regulator is disabled synchronous to the switching waveform. The shut off time will range between 4 and 8us. The standby LDO is capable of supporting up to 450mA of load. The standby LDO receives it's input from either the 3.3V Standby rail or the 5V Standby rail through the P3V3SBY pin. It is recommended that the 3.3V Standby rail be used as the power dissipation will be minimized. Sleep to Active (S3 to S0 Transition) When SLP_S3 transitions from LOW to HIGH with SLP_S5 still HIGH and after the 12V rail exceeds POR, the ISL6532 will enable the VDDQ switching regulator, disable the VDDQ
PGOOD
5V/DIV
2048 Clock Cycles
12V POR
PGOOD Comparator Enabled
FIGURE 3. TYPICAL S3 to S0 STATE TRANSITION
Active to Shutdown (S0 to S5 Transition) When the system transitions from active, S0, state to shutdown, S5, state, the ISL6532 IC disables all regulators and forces the PGOOD pin and the NCH pin LOW.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. Figure 4 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown in Figure 4 should be located as close together as possible. Please note that the capacitors CIN and CO may each represent numerous physical capacitors. Locate the ISL6532 within 3 inches of the MOSFETs, Q1 and Q2 . The circuit traces
9
ISL6532A
break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC .
VIN
ISL6532
UGATE Q1
Modulator Break Frequency Equations
LO VOUT
F
LC
1 = -----------------------------------------2 x L O x C O
F
ESR
1 = ------------------------------------------2 x ESR x C O
LOAD
LGATE
Q2
CIN CO
RETURN
FIGURE 4. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS
for the MOSFETs' gate and source connections from the ISL6532 must be sized to handle up to 1A peak current.
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO).
OSC PWM COMPARATOR VOSC DRIVER VIN LO DRIVER PHASE CO VOUT
The compensation network consists of the error amplifier (internal to the ISL6532ISL6532) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter's Double Pole (~75% FLC). 3. Place 2ND Zero at Filter's Double Pole. 4. Place 1ST Pole at the ESR Zero. 5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier's Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
1 F Z1 = ----------------------------------2 x R 2 x C 1 1 F Z2 = -----------------------------------------------------2 x ( R 1 + R 3 ) x C 3 1 F P1 = ------------------------------------------------------- C 1 x C 2 2 x R 2 x --------------------- C 1 + C2 1 F P2 = ----------------------------------2 x R 3 x C 3
-
+
ZFB VE/A +
ESR (PARASITIC)
-
ZIN REFERENCE
ERROR AMP
DETAILED COMPENSATION COMPONENTS C2 C1 R2 ZFB ZIN C3 R1 FB R3 VOUT
COMP
+
Figure 6 shows an asymptotic plot of the DC-DC converter's gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.
ISL6532
REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole 10
ISL6532A
Output Inductor Selection
100 80 60 GAIN (dB) 40 20 0 -20 -40 FLC -60 10 100 1K 10K FESR 100K 1M 10M MODULATOR GAIN 20LOG (R2/R1) OPEN LOOP ERROR AMP GAIN FZ1 FZ2 FP1 FP2
20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
I = VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6532 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. DDR memory systems are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the upper MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of upper MOSFET and the source of lower MOSFET. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a
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ISL6532A
conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. The maximum RMS current required by the regulator may be closely approximated through the following equation:
I RMS = V IN - V OUT V OUT V OUT 2 1 ------------- x I OUT + ----- x ---------------------------- x ------------- 12 L x f s V IN V IN MAX
2
package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. MOSFET Losses
2 1 P UPPER = Io x r DS ( ON ) x D + -- Io x V IN x t SW x F S 2
MAX
PLOWER = Io2 x rDS(ON) x (1 - D) Where: D is the duty cycle = VOUT / VIN , tSW is the combined switch ON and OFF time, and FS is the switching frequency.
For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested.
MOSFET Selection/Considerations
The ISL6532 requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see the equations below). These equations assume linear voltagecurrent transitions and do not adequately model power loss due the reverse-recovery of the upper and lower MOSFET's body diode. The gate-charge losses are dissipated by the ISL6532 and don't heat the MOSFETs. However, large gatecharge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to
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ISL6532A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L28.6x6
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 3.95 3.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 6.00 BSC 5.75 BSC 4.10 6.00 BSC 5.75 BSC 4.10 0.65 BSC 0.60 28 7 7 0.60 12 0.75 0.15 4.25 4.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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